Legal fence
Helion is an original FPGA family and CAD, not a wrapper around a vendor tool. Vendor user guides are a checklist of capabilities, not a source tree to copy. Device facts come from HAD, never hardcoded in the CAD. No vendor bitstream.
Do not add Project X-Ray, vendor Tcl, UNISIM names, or 7-series / UltraScale / Lattice / Intel bitstream backends.
Do not ship AXI interconnect as Helion IP. The buses are Helion-MM and Helion-ST.
Do not use vendor trademarks as product names in the UI or docs.
What is original
- HAD parts (
HL10T-C32-1and kin) and FeatureMap frames - HNF netlist, Session Tcl,
.hbits,.hckp - helion-sim / helion-fabric / IEEE 1149.1 TAP in helion-hw
- The desktop IDE as an eframe shell over
IdeModel
License
Dual Apache-2.0 OR MIT, your choice.
Security
RCE, path traversal, secrets: private advisory or @saksham-45. QoR misses and “does not fit Ibex on HL10T” are not vulnerabilities. See SECURITY.md.