Helion

Roadmap (1.4 to 2.0 shipped; 2.0.x grind)

FM-HEL-14. Original FPGA family plus in-repo CAD. Gold lock: empty-XDC examples/counter.sv stays WNS_PS=9640 on every step. Current release: v2.0.4. Canonical markdown: ROADMAP.md. GitHub: milestones.

ReleaseStatusWorkersWhatMilestone
1.4 shipped W1 SystemVerilog elaborator; gold 9640 1.4
1.5 shipped W2 + W4 PNR/STA + project/CLI 1.5
1.6 shipped W5 + W3 IDE + lab 1.6
1.7 shipped W6 + W8 VHDL + HAD 1.7
2.0 shipped Public OSS CAD bar (v2.0.0) 2.0
2.0.x current Post-bar STA / bitgen / place-legalize / synth / parse opt; gold lock unchanged v2.0.4

CI (W7) is not a product release. It gates gold on Ubuntu and macos-latest (both require WNS_PS=9640).

1.4: SV elaborator (W1)

Lower public-widen SOFT: always / case / functions / memories / generates onto Helion LUT/FF. Ports-only shells stay cells=0 / no_body. SOFT ≠ PASS. Gold WNS_PS=9640.

1.5: PNR/STA (W2) + project/CLI (W4)

Timing-driven place/route must move closed WNS (sites/hops). Constraint commands come from helion-sta::load_xdc (Architecture). Tcl Session CAD is a separate list. Restartable .prj / .hckp.

1.6: IDE (W5) + lab (W3)

Desktop helion-ide chrome without mixing hang work into elaborator commits. Lab: native FTDI / OFL STAT TDO DONE=1, then a real LED. No invented TAP STAT.

1.7: VHDL (W6) + HAD (W8)

VHDL-2008 elaborator on the same LUT/FF path as SV. HAD parts beyond HL10T-C32-1. Device facts stay in TOML.

2.0: public OSS CAD bar

Shipped as v2.0.0. A stranger can clone, cargo test --workspace, run headless gold WNS_PS=9640, and trust the legal fence.

2.0.x: post-bar runtime / QoR grind

Current tip: v2.0.4. Patch line after the 2.0 bar: measured STA / bitgen / place-legalize / synth_rtl / parse cuts without moving gold. SOFT ≠ PASS. Empty-XDC counter stays WNS_PS=9640. Release helion impl examples/ibex_pin_wrap.sv deltas: parse 416→353 ms, synth_rtl 670→524 ms, place legalize 213→23 ms, imux_skip 158→123. Table: docs/perf-2.0.4.md.

ROADMAP.md GitHub milestones Get involved