Helion

Using Helion

This is the user guide for the desktop IDE (helion-ide / Helion.app) and the CLI (helion). Build and download steps live on Start. The part is HL10T-C32-1 from HAD, not a vendor die.

What you get

Flags that never open a window: helion-ide --version, --doctor, --headless [file.sv], --stdin, --help.

Desktop IDE

  1. open dist/Helion.app, or cargo run -p helion-gui --bin helion-ide.
  2. Open HDL with the toolbar Open control (native file dialog via rfd) or the examples rail: counter.sv, blinky.sv, hier.sv, complex.sv, ysyx_ibex.sv.
  3. Run Implement (or the Synth / Opt / Place / Route / Bitstream chips). CAD jobs run on a helion-engine thread, not inside an egui frame.

Chrome is three canvases plus a 88 px activity rail. Rail items show a letter above the full name:

RailOpens
FilesEditor canvas: source in the main pane
DeviceDie floorplan of HL10T-C32-1 (IO ring, clock spine, CLB array). Package and Bitstream sit with it.
TimingSTA / Timing Summary in the center. Reports catalog stays in the sidebar.
SimulateWave traces. Does not leave the Timing tab selected.
ProgramHardware / ILA. Empty ILA fills the remaining pane. openFPGALoader is not shelled on every paint frame.
ReportsCatalog in the sidebar; the selected report in the center.

More (⋯) is overflow, at most two clicks away. Destinations include Schematic, Package, Bitstream, IP, Constraints, Summary, Settings, Find, DRC, Power, Utilization, Methodology, Hierarchy, Clock networks, CDC, Hardware, Wave, Memory, Breakpoints. More destinations never fall through to Timing. Schematic unconnected pins autohide unless the cell is selected.

Toolbar Open, flow chips, Bitstream, and Implement share one control height (36 px). The bottom console is Tcl. Splitters for sidebar and console are real grips.

Headless (no window). This is the gold gate:

cargo run -p helion-gui --bin helion-ide -- --headless examples/counter.sv
# expect: WNS_PS=9640

CLI

helion --version
helion doctor
helion gui
helion synth <file.sv> [--part P]
helion impl <file.sv> [--part P]
helion run <file.sv> [--cycles N] [--part P]
helion report_timing <file.sv> [--sdc f.sdc]
helion report_utilization <file.sv>
helion bitstream <file.sv|.vhd|.c|.prj> -o out.hbits
helion eco <file.sv> --cell u_lut --init 0xAAAAAAAAAAAAAAAA
helion pblock <file.sv>
helion qor <file.sv>
helion project <file.prj>
helion project run <file.prj> [--cycles N]
helion ip list|show <file.helion>|pack <name>
helion hnf <file.sv> [-o out.hnf]
helion hw list|detect
helion hw program|flash --cable auto|sim|usb|ofl|native [--bitstream FILE.hbits] [--part P]

Default part is HL10T-C32-1. From a checkout:

cargo run -p helion-cli -- doctor
cargo run -p helion-cli -- run examples/counter.sv --cycles 16
cargo run -p helion-cli -- report_timing examples/blinky.sv
cargo run -p helion-cli -- qor examples/counter.sv

helion gui execs the sibling helion-ide / Helion binary. helion doctor prints the compile-time target triple, rustc, runtime HAD path, CLB/IOB site counts, and FeatureMap text.

What gold means

Empty-XDC examples/counter.sv on a 10.000 ns clock: 4 LUTFF, 1 IOB, WNS_PS=9640, 185-byte sparse .hbits. The other gold designs also use 1 IOB. Fabric LED over 16 cycles: LED[16]=0000000111111110 (LED = cnt[3]).

DesignLUTFFWNS_PS.hbits B
blinky.sv19700153
counter.sv49640185
hier.sv19700153

If you change CAD or GUI, helion-ide --headless examples/counter.sv must still print WNS_PS=9640 unless the same commit updates the QoR table in the repository README with a reason. helion qor fails above 2000 ms wall time for these examples.

Device (the die)

HAD grid for HL10T-C32-1:

IO ring · 32 user IO IO CLK x=1 32 × 32 CLB HL10T-C32-1
WNS_PS=9640 · clk 10.000 ns · CAD reads devices/helion/parts/HL10T-C32-1.toml

Grid: x=0 IO, x=1 CLK spine, x=2..33 CLB, x=34 IO; y=0 IO, y=1..32 interior, y=33 IO. 8 BLE per CLB, 8 global clocks, 8 BRAM18, speed 1, idcode 0x00011A1F. In the app, Device is a canvas that fills the remaining pane, not a tiny bottom scroller.

Tcl Session

CAD Session, separate from XDC load_xdc. The console in helion-ide and helion-proj run the real engines. Commands: synth_design, opt_design, place_design, route_design, write_bitstream, write_hnf, get_cells / get_nets / get_pins, set_property, report_timing, report_utilization, open_hw_manager, program_hw, mark_debug, eco, write_checkpoint, report_die. .hckp restore must reproduce the same bitstream hash.

XDC (load_xdc)

Constraint text is parsed by load_xdc in crates/helion-sta/src/lib.rs. The command list (only those first-token arms) lives on Architecture. Not a vendor constraint product. Empty-XDC gold stays WNS_PS=9640.

IP packages (.helion)

Format-1 text manifests beside catalog HDL (ip/h_gpio, ip/h_uart, ip/h_rv32_hb1). Bus is Helion-MM / Helion-ST only. In the IDE, IP chips wrap; read_ip in a .prj loads a package. 

helion ip list
helion ip show ip/h_gpio/h_gpio.helion
helion ip show examples/ip/counter
helion project examples/ip_ingest/counter_ip.prj
helion project run examples/ip/read_ip_counter.prj --cycles 16

ILA (mark_debug to implement to ila_arm)

Mark a net, re-implement, then arm. Probe insert is idempotent after mark_debug.

mark_debug cnt_3
# Place, Route, Bitstream (or Implement)
ila_window 8
ila_arm cnt_3

Program / mpsse-sim / OFL

Without a USB programmer, detect stays 0 probes and refuses DONE. Never invent Helion TAP STAT. Never claim board DONE without live TDO evidence. 

./scripts/ibex-prog-mpsse-sim-smoke.sh
helion-prog --detect
helion hw detect
helion hw program --cable sim --bitstream out.hbits

macOS OFL (OSS): brew install openfpgaloader. Install is not DONE; you still need live FTDI plus Helion TAP STAT TDO. Cap holds on Ibex pin-wrap: imux_skip=0, IOB=1, gold WNS_PS=9640.

Large SystemVerilog

examples/ysyx_ibex.sv is on the Open rail. Ingest is helion-sv preprocess + parse. Fitting a full SoC on this part is not the synth bar. Leftover Helion-legal constructs should still map; do not abort the run because sv-parser is unhappy.

Build from source Architecture Roadmap